サブレンジングＡＤ変換入門 その２
Subranging, Error Corrected,
and Pipelined ADCs
Microsoft Word - Chapter 3 Data Converter Architectures F.doc (analog.com)
の
Subranging, Error Corrected, and Pipelined ADCsの部分のかなりおおざっぱ翻訳である。Ｐ３－６1～Ｐ３－７７
ＤＡ，ＡＤ変換解説 - SonofSamlawのブログ (hatenablog.com)
の３を参照
まだかきかけです。進めてまいります。
サブレンジング（パイプライン）ＡＤ変換入門 その１ - SonofSamlawのブログ (hatenablog.com)
からの続きです。
Modern digitally corrected subranging ADCs generally obtain the additional quantization
levels by using an internal ADC with higher resolution for the N2 SADC. For instance, if
one additional bit is added to the N2 SADC, its range is doubled—then the residue
waveform can go outside either end of the range by ½ LSB referenced to the N1 SADC.
Adding two extra bits to N2 allows the residue waveform to go outside either end of the
range by 1½ LSBs referenced to the N1 SADC. The residue waveform is offset using
Horna's technique such that only a simple adder is required to perform the correction
logic. The details of how all this works are not immediately obvious, and can best be
explained by going through an actual example of a 6-bit ADC with a 3-bit MSB SADC
and a 4-bit LSB SADC providing one bit of error correction. The block diagram of the
example ADC is shown in Figure 3.70.
【以上訳】
上の Hornaのテクニックを図３．７０により説明している。６ ｂｉｔＡＤＣである。３ ｂｉｔ ＭＳＢ ＳＡＤＣ と４ ｂｉｔ ＬＳＢ ＳＡＤＣで、誤差訂正のための１ ｂｉｔ を含む。
After passing through an input sample-and-hold, the signal is digitized by the 3-bit
SADC, reconstructed by a 3-bit SDAC, subtracted from the held analog signal and then
amplified and applied to the second 4-bit SADC. The gain of the amplifier, G, is chosen
so that the residue waveform occupies ½ the input range of the 4-bit SADC. The 3 LSBs
of the 6-bit output data word go directly from the second SADC to the output register.
The MSB of the 4-bit SADC controls whether or not the adder adds 001 to the 3 MSBs.
The carry output of the adder is used in conjunction with some simple overrange logic to
prevent the output bits from returning to the all-zeros state when the input signal goes
outside the positive range of the ADC.
【以上訳】
ここで、図３．７０で∑において±が逆になっている。正しくはアナログーＳＤＡＣである。
説明は上と同じ。
The residue waveform for a full-scale ramp input will now be examined in more detail to
explain how the correction logic works. Figure 3.71 shows the ideal residue waveform
assuming perfect linearity in the first ADC and perfect alignment between the two stages.
Notice that the residue waveform occupies exactly ½ the range of the N2 SADC. The 4-
bit digital output of the N2 SADC are shown on the left-hand side of the figure. The
regions defined by the 3-bit uncorrected N1 SADC are shown on the bottom of the figure.
The regions defined by the 3-bit corrected N1 ADC are shown are shown at the top of the
figure.
【以上訳】
図3.71は６ ｂｉｔ、 ＡＤＣの完全なＭＳＢの誤差値波形を示している。
Following the residue waveform from left-to-right—as the input first enters the overall
ADC range at –FS, the N2 SADC begins to count up, starting at 0000. When the N2
SADC reaches the 1000 code, 001 is added to the N1 SADC output causing it to change
from 000 to 001. As the residue waveform continues to increase, the N2 SADC continues
to count up until it reaches the code 1100, at which point the N1 SADC switches to the
next level, the SDAC switches and causes the residue waveform to jump down to the
0100 output code. The adder is now disabled because the MSB of the N2 SADC is zero,
so the N1 SADC output remains 001. The residue waveform then continues to pass
through each of the remaining regions until +FS is reached.
【以上訳】
This method has some clever features worth mentioning. First, the overall transfer
function is offset by ½ LSB referred to the MSB SADC (which is 1/16th FS referred to
the overall ADC analog input). This is easily corrected by injecting an offset into the
input sample-and-hold. It is well-known that the points at which the internal N1 SADC
and SDAC switch are the most likely to have additional noise and are the most likely to
create differential nonlinearity in the overall ADC transfer function. Offsetting them by
1/16th FS ensures that low level signals (less than ±1/16th FS) near zero volts analog
input do not exercise the critical switching points and gives low noise and excellent DNL
where they are most needed in communications applications. Finally, since the ideal
residue signal is centered within the range of the N2 SADC, the extra range provided by
the N2 SADC allows up to a ±1/16th FS error in the N1 SADC conversion while still
maintaining no missing codes.
【以上訳】
Figure 3.72 shows a residue signal where there are errors in the N1 SADC. Notice that
there is no effect on the overall ADC linearity provided the residue signal remains within
the range of the N2 SADC. As long as this condition is met, the error correction method
described corrects for the following errors: sample-and-hold droop error, sample-andhold
settling time error, N1 SADC gain error, N1 SADC offset error, N1 SDAC offset
error, N1 SADC linearity error, residue amplifier offset error. In spite of its ability to
correct all these errors, it should be emphasized that this method does not correct for gain
and linearity errors associated with the N1 SDAC or gain errors in the residue amplifier.
The errors in these parameters must be kept less than 1 LSB referred to the N-bits of the
overall subranging ADC. Another way to look at this requirement is to realize that the
amplitude of the vertical transitions of the residue waveform, corresponding to the N1
SADC and SDAC changing levels, must remain within ±½ LSB referenced to the N2
SADC input in order for the correction to prevent missing codes.
【以上訳】
Figure 3.73 shows two methods that can be used to design a pipeline stage in a
subranging ADC. Figure 3.73A shows two pipelined stages which use an interstage T/H
in order to provide interstage gain and give each stage the maximum possible amount of
time to process the signal at its input. In Figure 3.73B a multiplying DAC is used to
provide the appropriate amount of interstage gain as well as the subtraction function.
【以上訳】
The term "pipelined" architecture refers to the ability of one stage to process data from
the previous stage during any given clock cycle. At the end of each phase of a particular
clock cycle, the output of a given stage is passed on to the next stage using the T/H
functions and new data is shifted into the stage. Of course this means that the digital
outputs of all but the last stage in the "pipeline" must be stored in the appropriate number
of shift registers so that the digital data arriving at the correction logic corresponds to the
same sample.
【以上訳】
Figure 3.74 shows a timing diagram of a typical pipelined subranging ADC. Notice that
the phases of the clocks to the T/H amplifiers are alternated from stage to stage such that
when a particular T/H in the ADC enters the hold mode it holds the sample from the
preceding T/H, and the preceding T/H returns to the track mode. The held analog signal
is passed along from stage to stage until it reaches the final stage in the pipelined ADC—
in this case, a flash converter. When operating at high sampling rates, it is critical that the
differential sampling clock be kept at a 50% duty cycle for optimum performance. Duty
cycles other than 50% affect all the T/H amplifiers in the chain—some will have longer
than optimum track times and shorter than optimum hold times; while others suffer
exactly the reverse condition. Several newer pipelined ADCs including the 12-bit, 65-
MSPS AD9235 and the 12-bit, 170-/210-MSPS AD9430 have on-chip clock conditioning
circuits to control the internal duty cycle while allowing some variation in the external
clock duty cycle.
【以上訳】
The effects of the "pipeline" delay (sometimes called latency) in the output data are
shown in Figure 3.75 for the AD9235 12-bit 65-MSPS ADC where there is a 7-clock
cycle pipeline delay.
【以上訳】
Note that the pipeline delay is a function of the number of stages and the particular
architecture of the ADC under consideration—the data sheet should always be consulted
for the exact details of the relationship between the sampling clock and the output data
timing. In many applications the pipeline delay will not be a problem, but if the ADC is
inside a feedback loop the pipeline delay may cause instability. The pipeline delay can
also be troublesome in multiplexed applications or when operating the ADC in a "single-
shot" mode. Other ADC architectures—such as successive approximation—may be better
suited to these types of applications.
【以上訳】
３－６９最後
